Nihal Singh

Founding Research Engineer, Flucta AI

Ph.D. in Computer Engineering from UC Santa Barbara, U.S. Citizen

Building the next generation of energy-efficient AI through hardware–software co-design, from accelerator architecture to LLM inference.

Download CV (PDF, opens in a new tab)

Fig. 1 Live

A grid of interacting spins (a 2-D Ising model) just above its critical temperature, sampled by simulated p-bits. Dots are up-spins; bare paper is down-spins.

About

Portrait of Nihal Singh

I am a U.S. Citizen with a Ph.D. in Computer Engineering from UC Santa Barbara, passionate about building the next generation of AI systems.

My work sits at the intersection of machine learning, computer architecture, and systems engineering. I am interested in AI hardware–software co-design, efficient inference, accelerator architectures, CUDA optimization, and scalable infrastructure for large-scale AI.

My doctoral research spans diffusion models, probabilistic machine learning, and energy-efficient accelerator design, with a focus on translating machine learning algorithms into practical, high-performance computing systems.

I am excited by opportunities to help shape the future of AI infrastructure through close integration of algorithms, software, and hardware.

Focus areas

  • AI hardware–software co-design
  • Efficient LLM inference
  • Optimized accelerator architectures
  • CUDA optimization
  • Physics-inspired diffusion models
  • Probabilistic computing

Education

Ph.D.
Electrical and Computer Engineering, UC Santa Barbara (UCSB)
M.S.
Electrical and Computer Engineering, UC Santa Barbara (UCSB)
B.E. (Hons.)
Electrical and Electronics Engineering, Birla Institute of Technology and Science (BITS), Pilani, India

What I offer

  1. AI/ML

    • Efficient LLM inference and diffusion models
    • Probabilistic, physics-inspired machine learning

  2. Algorithms

    • Hardware-aware Monte Carlo sampling and optimization solvers
    • Energy-based and physics-informed models

  3. Systems

    • LLM and diffusion model hardware–software co-design
    • Heterogeneous accelerators (GPU/FPGA/sMTJ/CMOS/CPU)

  4. Circuits

    • Designing and prototyping probabilistic circuits
    • Analog/RF and digital ASIC design (Cadence, Spice, Verilog)

  5. Devices

    • Device–circuit co-design with sMTJs and CMOS

Publications

  1. From Independent to Correlated Diffusion: Generalized Generative Modeling with Probabilistic Computers (opens in a new tab)

    arXiv · 2026

    Figure from the paper: standard versus correlated diffusion noising on p-bit hardware, with red and blue spin lattices at successive noising steps.

  2. CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning (opens in a new tab)

    Nature Communications · 2024

    Figure from the paper: stochastic MTJ stack, sMTJ-based p-bit circuit, FPGA digital p-bits and the experimental hardware.

  3. Beyond Ising: Mixed Continuous Optimization with Gaussian Probabilistic Bits Using Stochastic MTJs (opens in a new tab)

    IEEE IEDM · 2024

    Figure from the paper: heterogeneous probabilistic computer built from sMTJ p-bits and CMOS with its experimental setup, synchronous versus asynchronous Gibbs sampling, and a Gaussian probabilistic bit. © 2024 IEEE

  4. Hardware Demonstration of Feedforward Stochastic Neural Networks with Fast MTJ-based p-bits (opens in a new tab)

    IEEE IEDM · 2023

    Figure from the paper: p-computing model, sMTJ circuit with FPGA design, and the sMTJ plus FPGA hardware setup, with unordered sMTJ clocks for Boltzmann-Ising machines and ordered clocks for Bayesian and feedforward networks. © 2023 IEEE

All publications on Google Scholar (opens in a new tab)

For more notes, ideas and projects (opens in a new tab)

Contact

Follow my research or reach out about collaborations.